Phase Change Memory Enters a New Phase 2nd Edition

Table of Contents

CONTENTS

LIST OF FIGURES

LIST OF TABLES

TERMINOLOGY

EXECUTIVE SUMMARY

MEMORY OVERVIEW

• Introduction
• The Memory Hierarchy
• SRAM
  • Concept
  • Technology Evolution
• DRAM
  • Concept
  • Technology Evolution
• NOR Flash
  • Concept
  • Technology Evolution
• NROM
  • Concept
  • Technology Evolution
• NAND Flash
  • Concept
  • Technology Evolution

PHASE CHANGE MEMORY

• Introduction
• Phase Change Material
• Memory Cell Concept
• Basic Operation
• Memory Cell Variations
• Selection Device
• PCM Characteristics
  • Set Time
  • Reset Current
  • Endurance
  • Memory Comparison
• Multi-level Cell PCM
• Device Layout
• PCM Reliability
• PCM Cost Drivers
  • Die Size
  • Process Complexity
• Technology Scaling
  • Scaling Parameters
  • Roadmap

PCM DEVELOPMENT STATUS

• PCM Development Status
• ATMI, Inc.
• BAE Systems
• CAMELS
• Elpida
• Hynix Semiconductor
• IBM
• IMEC
• ITRI
• Macronix International
• Nanochip
• Numonyx (Intel/ST)
• NXP Semiconductors
• Ovonyx
• Qimonda AG
• Renesas Technology
• Samsung Electronics
• STMicroelectronics
• ULVAC

MARKET FORECAST

• PCM as a NOR Replacement
• PCM as a Non-volatile RAM
• PCM as a Storage Class Memory
• Applications
• Embedded PCM
• Market

REFERENCES

ABOUT THE AUTHOR

ABOUT FORWARD INSIGHTS

• Services
• Contact

REPORT OFFERINGS

List of Figures

• Figure 1. Memory Hierarchy
• Figure 2. SRAM Cell Layout
• Figure 3. 3D SRAM Technology
• Figure 4. DRAM Cell
• Figure 5. DRAM Cell Transistor Evolution
• Figure 6. DRAM Cell Capacitor Trend
• Figure 7. NOR Flash Cell
• Figure 8. NOR Architecture
• Figure 9. NOR Flash Cell
• Figure 10. NOR Flash Technology Evolution
• Figure 11. Drain Bias Margin
• Figure 12. NROM Cell Concept
• Figure 13. NROM Architecture
• Figure 14. NROM Cell
• Figure 15. NROM Technology Evolution
• Figure 16. Bit Disturb (“Second Bit Effect”)
• Figure 17. NAND Flash Cell Concept
• Figure 18. NAND Architecture
• Figure 19. NAND Cell String
• Figure 20. NAND Flash Technology Evolution
• Figure 21. NAND Flash Memory Gap Fill
• Figure 22. Electrons Stored on the Floating Gate
• Figure 23. Samsung 32Gb CTF Memory
• Figure 24. Timeline of Phase Change Memory
• Figure 25. Periodic Table
• Figure 26. GST Composition
• Figure 27. Basic PCM Cell Structure
• Figure 28. Set Operation
• Figure 29. Reset Operation
• Figure 30. Phase Change Memory I-V Curve
• Figure 31. Memory Array Operation
• Figure 32. μTrench and Lance Structures
• Figure 33. Lance and pore structure
• Figure 34. Phase Change Bridge Memory
• Figure 35. MOS and BJT Selector
• Figure 36. Diode Selector
• Figure 37. Set Time Trend
• Figure 38. Dependence of Reset Current on Contact Area
• Figure 39. Reset Current Reduction with Ta2O5 Interfacial Layer
• Figure 40. Reset Current Trend
• Figure 41. PCM Endurance
• Figure 42. Read Access Time Comparison
• Figure 43. Write Throughput
• Figure 44. Program Performance Comparison
• Figure 45. MLC Write Approaches
• Figure 46. MLC Distribution
• Figure 47. Multi-level States as a Function of Pulse Tail
• Figure 48. 16-Level and 4-Level PCM
• Figure 49. Samsung Phase Change Memory Device Evolution
• Figure 50. Samsung 90nm 512Mb PRAM Layout
• Figure 51. ST/Intel Phase Change Memory Device Evolution
• Figure 52. NOR Flash and PCM Architecture
• Figure 53. Intel 256Mb 130nm 28F256L18 StrataFlash Organization
• Figure 54. 128Mb (256Mb MLC) PCM Organization
• Figure 55. Endurance as a function of Energy per Pulse
• Figure 56. PCM vs. NOR Flash
• Figure 57. Phase Change Memory Technology Evolution
• Figure 58. Samsung PRAM Cell Size Evolution
• Figure 59. SABEC Process
• Figure 60. PRAM Module
• Figure 61. 180nm Process μTrench PCM Process
• Figure 62. Phase Change Memory with μTrench Cell
• Figure 63. Scaling Parameters
• Figure 64. PCM Scaling Challenges
• Figure 65. Memory Roadmaps
• Figure 66. Bit Size Trend
• Figure 67. Density Trend
• Figure 68. Areal Density Trend
• Figure 69. Embedded PCM Roadmap
• Figure 70. U.S. PCM Patents from 1990 to January 2007
• Figure 71. Radition-hard C-RAM
• Figure 72. Memory Device Characteristics - 2012
• Figure 73. PCM in the Memory System
• Figure 74. Hybrid FTL for NAND/PCM
• Figure 75. SCM Target Specifications
• Figure 76. Enterprise Data Systems Memory & Storage
• Figure 77. SCM Address Translation
• Figure 78. PCM as an Unified Memory
• Figure 79. PCM in the Memory Hierarchy
• Figure 80. $/MB Forecast
• Figure 81. PCM NOR Replacement Rate
• Figure 82. Enterprise DRAM TAM
• Figure 83. Memory Revenue Forecast

List of Tables

• Table 1. Memory Comparison
• Table 2. PCM Development Status