Key Parameters of Stacked Cross-Point Array Memory
Bit Size
Process Complexity
Cell Efficiency
Yield
Performance
Endurance
Power Consumption
Scalability
Cost
Summary
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List of Figures
Figure 1. NAND Flash Technology Evolution
Figure 2. NAND Flash Memory Gap Fill
Figure 3. NAND Flash Memory Coupling Ratio and Cross-talk
Figure 4. Electrons Stored on the Floating Gate
Figure 5. Samsung 32Gb CTF Memory
Figure 6. Estimation of NAND fabrication costs as the bit density
increases for conventional planar and stacked cell
Figure 7. Schematic cross section of the 3-D TANOS NAND showing a first
arrangement of strings on Si substrate level and a second level of NAND memory
cell strings stacked above
Figure 8. SEMs of 3D stacked NAND cell string. The 2nd active layer is
SOI-like perfect single crystal
Figure 9. Layout and vertical structure of word-lines and x-decoders for
the doubly stacked NAND flash memory cell array
Figure 10. Key process steps of 3D NAND memory
Figure 11. Comparison of erase operation (a) well bias initiated erase by
block, (b) erase by page without well bias in the floating body case
Figure 12. (a) TEM cross section image of LEG Si film; Inset image shows
sub-grain boundary protrusion. (b) Modelling of LEG process; selective melting
of a-Si film and solidification from seed
Figure 13. Process scheme with amorphous layer formation on seeds to
initiate laser epitaxial growth of single crystal Si film resulting in stacked
transistor bodies for 3D memories
Figure 14. Tilted SEM image with protrusions which are precisely located
in the center between neighbouring seeds
Figure 15. Tri-gate structure of the TFT device based SONOS memory cell
(Macronix)
Figure 16. TEM cross sections of TFT NAND strings perpendicular to the
wordline and along wordline direction
Figure 17. Schematic illustration of thermal budget impact on device
structure: S/D junctions between NAND wordlines diffuse below gate contacts
and cause punchthrough device failure
Figure 18. Simulated temperature profiles for various laser pulse
durations. The penetration depths can be controlled by the pulse durations
Figure 19. The basic concept of the DG-TFT-SONOS Flash showing
simultaneous shielding of stored charge during pass voltage application and
intimate electrical interaction for good short channel control
Figure 20. XTEM along NAND string channel of the dual gate SONOS devices
Figure 21. SIMS analysis of antimony-implanted LPCVD amorphous silicon
that subsequently underwent the illustrated thermal steps. This mimics the
behavior of the source and drain dopant during processing. Negligible
diffusion occurs
Figure 22. Sheet resistance of antimony implanted into LPCVD amorphous
silicon and annealed
Figure 23. Cycling endurance of the mid-cell of a 32 cell string of
minimum feature sized devices. No other second-gated memory devices are used
in the cycling
Figure 24. Retention after cycling 105 cycles showing good performance
after extrapolation to years
Figure 25. Equivalent circuit of the BiCS arrangement of vertical NAND
strings
Figure 26. Birds-eye view of BiCS flash memory. NCG is the number of
control gates. NSG is the number of rows of pillars sharing an upper select
gate
Figure 27. (a) Cross section of BiCS flash memory string, (b) Cross
section of vertical SONOS cell
Figure 28. Stair-like structure at the edge of control gate plates and
upper select gate pitch
Figure 29. Fabrication sequence of BiCS flash memory
Figure 30. Cross sectional SEM image and schematic illustration of the
latest reported BiCS cell array
Figure 31. Id-Vg characteristics after program and erase operation of each
of the different cells of a NAND string (non-optimized structure with respect
to disturb)
Figure 32. Schematic potential profile in unselected pillars during
program operation. The potential of pillars boosted by Vpgm is seen to be
higher than Vpass and a negative Vth shift of the cell to be programmed is
achieved
Figure 33. Vth shift after program disturb of programmed cells in
unselected pillars. A negative Vth shift is suppressed if suitable Vpass is
selected
Figure 34. Improved concept of changing lower select gate plates to line
and space pattern in order to boost unselected pillars by turning on/off USG
and LSG synchronously
Figure 35. Vth shift after read disturb on unselected pillars. Vth shift
is suppressed significantly by changing the lower select gate plates into line
and space patterns
Figure 36. Schematic illustration of SONS and SONONS memory layer scheme.
The tunnel film in the SONONS structure inhibits the release of trapped
charges of the trapping layer. Retention and disturb behavior is improved
Figure 37. Program and erase characteristics of SONONS based BiCS cells
Figure 38. Data retention results of SONONS and SONS cells of BiCS flash
Figure 39. This Besang picture shows an SEM (right) of the vertical memory
cells of a 10 kb flash memory array with schematics (left) depicting the
stacked memory and CMOS circuitry
Figure 40. Schematic of a PCM memory array with nanowire diodes as memory
cell select devices
Figure 41. (a) Shows a generalized cross-point memory structure whose one
bit cell of the array consists of a memory element and a switch element
between conductive lines on top (wordline) and bottom (bitline). (b)
Illustration of reading interference in an array consisting of 2 X 2 cells
without switch elements. (c) Rectified reading operation in an array
consisting of 2 X 2 cells with switch elements
Figure 42. Matrix 3D poly Si anti-fuse diode cell schematics and
electrical characteristics of programmed and unprogrammed cell
Figure 43. Matrix 3D poly Si anti-fuse diode cross section
Figure 44. Matrix 3D poly Si anti-fuse memory cross section
Figure 45. Cross section of the 512Mb PRAM with diodes as select devices
Figure 46. Process sequence for the vertical diode and the self aligned
bottom electrode contact (SABEC)
Figure 47. Simulated temperature profile while writing RESET state. The
temperature of the pn-junction in vertical diode is not too high to degrade the
device operation
Figure 48. Expected evolution of cell structures: Cross sections of the
PRAM switching elements
Figure 49. Simulated write current for melting at the phase transformation
core of (a) a conventional planar PCM and (b) a confined cell structure. When
the reset current is applied to the confined cell structure, melting of PCM is
expected to occur between electrodes limited to isolated cell
Figure 50. TEM images of dash-type confined cell structure. Even with
7.5nm width: The PCM was filled perfectly without voids
Figure 51. Endurance characteristic of confined PCM cell
Figure 52. Proposed resistance switching mechanism of RRAM. The Schottky
barrier is reversibly modulated by charging/discharging of vacancies
Figure 53. Left: Schematic potential energy diagram of the TaOx redox
pair: Δ G is the smallest of all commonly known resistive switching
material candidates indicating that both HRS and LRS are stable. Right:
Schematic change of the barrier height corresponding to the redox reaction
according to the model assumption
Figure 54. Cross section of fabricated 1T1R ReRAM cells based on 0.18μm
CMOS process
Figure 55. (a) Workfunction versus electrode potential of various
electrode metals and appearance of the switching effect, (b) switching
behaviour with Ir electrode and (c) with Pt electrode
Figure 56. (a) I-V plot of the 1T1R memory cell (cell area 0.5 x0.5
μm²) in pulse voltage sweep with 100ns pulse width, (b) Schottky plot of
I-V characteristic
Figure 57. Endurance properties of ReRAM (left) and data retention of TaOx
memory cells at 150°C (right)
Figure 58. Sketch of the cell cross section (top) and sample cross section
of the fabricated die with enlarged TEM (right),
Figure 59. I-V characteristic of a memory cell in sweeping mode
Figure 60. Read disturb characteristics for set and reset status with
-0.1 V bias forcing to reset and +0.1 V bias forcing to set, respectively. No
degradation is found up to 10³ seconds
Figure 61. Scaling characteristics of resistance distributions for (a) 50
nm diameter cells and (b) 20 nm diameter cells without verification loop. The
inset shows an AFM image of a 20 nm diameter cell
Figure 62. Schematic diagram of a 2-stack 1D-1R cell arrangement with
upper layers reversed to share the bitline. The line width of word and
bitlines was 0.5μm resulting in a final cell size of 0.5x0.5μm²
Figure 63. Conceptual schematic diagram of a stacked memory with TFTs
decoders as stackable peripheral circuits
Figure 64. Specifications for 43nm SLC and MLC NAND Flash
Figure 65. Lithography Resolution Limits
Figure 66. Relative Cost per Bit of Stacked SLC NAND
Figure 67. Relative Cost per Bit of Stackable Non-volatile Memories
List of Tables
Table 1. Multi-bit NAND Flash Comparison
Table 2. Comparison of Multilayer NAND with SLC NAND
Table 3. Comparison of Multilayer NAND with MLC NAND
Table 4. Comparison of BiCS NAND with SLC and MLC NAND
Table 5. Comparison of Stacked Cross Point Array Memory with SLC and MLC
NAND
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