Comparison of 3-bit per cell NAND Flash Memories

Table of Contents

• Contents
• List of Figure
• List of Tables
• Executive Summary
• Introduction
• Three-bit per cell NAND Flash Memories
  • SanDisk/Toshiba 56nm 16Gb 3-bit/cell NAND Flash Memory
    • Summary
    • Page Buffer
    • Page Organization
    • Cache algorithms
    • Source Line Bias Error Compensation
    • Power Routing Organization
    • Data Path
  • All Bitline vs. Interleaved Architecture
    • Program Speed
    • ABL - Considerations on Scalability
  • Hynix 48nm 32Gb 3-bit/cell NAND Flash Memory
    • Summary
    • Chip Architecture
    • Pass Bit Detector Circuits
    • Smart Blind Program Algorithm
    • Start Bias Controlled Program Algorithm
  • 32Gb 32nm 3-bit/cell SanDisk/Toshiba
    • Summary
    • Chip Architecture
    • Program Verify Read Before Programming
    • Compact Row Decoder
    • Extended Column Architecture
  • Samsung 51nm 16Gb 3-bit/cell NAND Flash Memory
    • Summary
  • Summary
• References
• About the Author
• About Forward Insights
  • Services
  • Contact
• Report Offerings

List of Figures

• Figure 1. NAND Flash Areal Storage Density Trend
• Figure 2. ISPP for 2-bit and 3-bit per cell Technology
• Figure 3. ABL architecture
• Figure 4. Page Organization and Programming
• Figure 5. Conventional Cache Program
• Figure 6. FSC +MCR
• Figure 7. Source line Bias Error: Ideal Case
• Figure 8. Source line Bias Error: Real Case
• Figure 9. Source line Bias Error: Source Tracking
• Figure 10. Chip comparison
• Figure 11. Power Bus Routing: 16Gb D2 vs. 16Gb x3 (rotated array)
• Figure 12. Data Path: 16Gb D2 vs 16Gb x3 (rotated array)
• Figure 13. Program speed improvements
• Figure 14. ABL Architecture with 8K Page Size Compared to Interleaved Architecture with 4KB Page Size
• Figure 15. ABL Architecture with 8K Page Size Compared to Interleaved Architecture with 8KB Page Size
• Figure 16. ABL Architecture vs. Interleaved Architecture: Double Sided Page Buffer
• Figure 17. BLC Line Density vs. Core Scalability
• Figure 18. 3-bit/cell NAND Flash Program Time
• Figure 19. Die micrograph of Hynix 32Gb 8LC NAND Flash Memory
• Figure 20. Pass Bit Detector
• Figure 21. Smart Blind Program
• Figure 22. Start Bias Controlled Program
• Figure 23. SanDisk/Toshiba 32nm 32Gb 3-bit/cell NAND Flash Die Micrograph
• Figure 24. Program Inhibit
• Figure 25. Schematic view of row decoder
• Figure 26. String Organization
• Figure 27. Endurance properties
• Figure 28. Current Degradation due to Series Resistance

List of Tables

• Table 1. Features Summary of SanDisk/Toshiba 56nm 16Gb 3-bit/cell NAND Flash Memory
• Table 2. ABL vs. Interleaving
• Table 3. Features Summary of Hynix 48nm 32Gb 3-bit/cell NAND Flash Memory
• Table 4. Features Summary of SanDisk/Toshiba 32nm 32Gb 3-bit/cell NAND Flash Memory
• Table 3. Features Summary of Samsung 51nm 16Gb 3-bit/cell NAND Flash Memory
• Table 5. Key Parameters Comparison
• Table 7. Key Features and Advantages & Disadvantages of SanDisk/Toshiba 56nm 16Gb 3- bit/cell NAND Flash Memory
• Table 8. Key Features and Advantages & Disadvantages of Hynix 48nm 32Gb 3-bit/cell NAND Flash Memory
• Table 9. Key Features and Advantages & Disadvantages of SanDisk/Toshiba 32nm 32Gb 3-bit/cell NAND Flash Memory
• Table 10. Key Features and Advantages & Disadvantages of Samsung 51nm 16Gb 3-bit/cell NAND Flash Memory