Table of Contents
Chapter 1 Introduction
Chapter 2 Executive Summary
Chapter 3 Flip Chip Issues and Trends
- 3.1 Introduction
- 3.2 Wafer Bumping
- 3.2.1 Solder Bumps
- 3.2.1.1 Metallurgy
- 3.2.1.2 Deposition Of UBM
- 3.2.1.3 Sputter Etching
- 3.2.1.4 Photolithography
- 3.2.1.5 Solder Deposition
- 3.2.1.6 Resist Strip
- 3.2.1.7 UBM Wet Etch
- 3.2.1.8 Reflow
- 3.2.1.9 Flux Issues
- 3.2.2 Gold Bumps
- 3.2.2.1 Bump Processing
- 3.2.2.2 Bonding
- 3.2.2.3 Coplanarity
- 3.2.2.4 Conductivity
- 3.2.2.5 Thermal Properties
- 3.2.2.6 Size
- 3.2.2.7 Reliability
- 3.2.2.8 Cost Issues
- 3.2.3 Copper Pillar Bumps
- 3.2.4 Copper Stud Bumping
- 3.2.5 C4NP
- 3.3 Wafer Level Packaging
- 3.4 Pad Redistribution
- 3.5 Wafer Bumping Costs
- 3.5.1 Wafer Redistribution And Wafer Bumping Costs
- 3.5.2 WLCSP Hidden Costs
- 3.5.3 WLCSP Cost Per Good Die
- 3.5.4 Wafer-Level Underfill Costs
Chapter 4 Lithography Issues And Trends
- 4.1 Issues4-1
- 4.1.1 Technical Performance
- 4.1.2 Capital Investment
- 4.1.3 Cost Of Consumables
- 4.1.4 Throughput
- 4.1.5 Ease Of Use
- 4.1.6 Flexibility
- 4.1.7 Equipment Support
- 4.1.8 Resolution
- 4.1.9 Solder Bumping Capabilities
- 4.1.10 Gold Bumping Capabilities
- 4.2 Exposure Systems
- 4.2.1 Introduction
- 4.2.1.1 Reduction Steppers
- 4.2.1.2 Full-Field Projection
- 4.2.1.3 Mask Aligners
- 4.2.1.4 1x Steppers
- 4.3 Competitive Technologies
- 4.3.1 Inkjet Printing
- 4.3.2 Stencil/Screen Printing
- 4.3.3 Electroless Metal Deposition
Chapter 5 UBM Etch Issues And Trends
- 5.1 Introduction
- 5.2 Technology Issues And Trends
- 5.2.1 Process Flow
- 5.2.2 Etch Process
- 5.2.3 Etch Chemistry
- 5.3 Batch Versus Single-Wafer Etching
Chapter 6 Market Analysis
- 6.1 Market Drivers For Flip Chip And Wlp
- 6.1.1 WLP For Small Die
- 6.1.2 WLP For Medium Die
- 6.1.3 WLP For Large Die
- 6.2 Market Opportunities
- 6.3 Challenges
- 6.4 Flip Chip Market
- 6.5 Lithography Market
- 6.5.1 Aligners Vs. Steppers
- 6.5.2 Market Analysis
- 6.6 Wet Etch Market
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