Abstract
Future etch technology development, in support of future projected BEOL
requirements, will include both dielectric and conductor classes of materials.
Continual optimization of existing capacitively coupled based source
technology is envisioned to adequately address the progression of shrinking
line/space dimensions and associated via/contact diameters while overall
aspect ratios maintain parity with current technology. Future memory
technology development will require the introduction of progressively higher
dielectric materials to partially offset cell area reductions. These materials
as a class exhibit very low volatility by-products. The high aspect ratio
contact etch is expected to be continually challenged based on ever increasing
aspect ratios for each new technology node. It is anticipated that current
inductively coupled source equipment will continue to address future needs.
Conductor etch requirements include the continuation of the stalwart Al etch,
to at least the 90 nm technology node using existing inductively coupled
plasma source technology. The introduction of progressively higher dielectric
materials in support of future memory technology development are also
anticipated to require new top and bottom metal electrode materials like noble
and refractory metals. Currently, etch of these metal electrode materials are
being addressed with existing capacitively coupled source equipment.
New interconnect and/or package technologies (e.g., 3D IC) are moving into
manufacturing. One of the key technology challenges of this technology is the
need to etch 100 micron vias from the interconnect layers, through the entire
wafer providing for electrical (or sometimes thermal) connections on the back
of the die. The use of Xenon containing gas mixtures will be critical.
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